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2-channel, 12-bit adc with i 2 c-compatible interface in 10-lead msop ad7992 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features 12-bit a d c wit h fast conversi on time: 2 s t y p 2 single-en ded analog input channels specified for v dd of 2.7 v to 5. 5 v low power con s umption fast throughput rate: up to 1 88 ksps sequencer ope r ation temperature r a nge: ? 40 c to 125 c au tomatic cy cle mode i 2 c?-compatibl e serial interfac e supports stan dard, f a st, and high spee d mo des out-of-range i n dicator/alert f u nction pin-selectable addressing via as 2 versions a llow 5 i 2 c ad dress e s shutdown mode: 1 a max 10-lea d msop package general description the ad7992 is a 12-b i t, lo w p o w e r , s u cces si v e a p p r o x ima t io n ad c wi t h an i 2 c-co m p a t ib le i n t e r f ac e . th e p a r t o p era t es f r o m a sin g le 2.7 v t o 5.5 v p o w e r s u p p l y a n d f e a t ur es a 2 s co n v er - s i on t i me. t h e p a r t c o n t ai ns a 2 - ch an nel m u lt ipl e xe r and t r a c k - a nd- h o ld am pli f ier t h a t can han d l e i n p u t f r e q uen c ies u p to 11 mh z. the ad7992 p r o v ides a 2 - wir e s e r i al in t e r f ace co m p a t i b le wi th i 2 c in t e r f aces. th e p a r t com e s in tw o v e rsio n s , th e ad7992-0 a nd t h e a d 799 2-1, a nd e a ch ve rsio n a l lo ws fo r a t le ast tw o dif f er en t i 2 c addr es s e s. the ad7992-0 s u p p or ts s t a nda rd and fas t i 2 c in t e r f ac e m o des, and t h e ad7992-1 s u p p o r ts s t a n da r d , fast, and hig h sp e e d i 2 c in t e r f ace mo des. the ad7992 n o r m al l y r e ma in s in a s h u t do wn sta t e while n o t co n v er t i ng, and p o w e rs u p o n l y fo r co n v ersio n s. the con v ersio n p r o c es s ca n b e c o n t r o l l e d usin g t h e co n v s t p i n, b y a co mman d m o de w h er e con v ersio n s o c c u r acr o s s i 2 c wr i t e op e r a t i o ns , or a n a u tom a t i c c o n v e r s i on i n te r v a l mo d e s e l e c t e d t h rou g h s o f t w a r e c o n t ro l. the ad7992 r e q u ir es a n ext e r n al r e f e r e n c e in t h e ra n g e o f 1.2 v to v dd . this a l l o ws t h e wi dest d y na mic in p u t r a n g e t o t h e ad c. on-ch i p li mi t reg i sters can b e p r o g r a mm e d wi t h hi g h and lo w l i m i t s f o r t h e c o n v e r s i on re su lt , an d an o p e n - d r a i n , out - of - ra n g e i n di ca t o r o u t p ut (aler t ) b e com e s ac t i ve w h en t h e co n v ersio n r e s u l t viola t e s t h e p r og ra mm e d hig h o r lo w limi ts. t h i s ou tput c a n b e u s e d a s an i n te r r upt . func tio n a l block di agram control logic ad7992 v dd scl conversion result register cycle timer register alert status register sda gnd a ler t 03263- 0- 001 gnd convst as v in 1 v in 2/ref in data high limit register ch1 data high limit register ch2 data low limit register ch2 data low limit register ch1 hysteresis register ch1 hysteresis register ch0 i/p mux t/h i 2 c interface configuration register 12-bit successive approximation adc vin2/refin software control fi g u r e 1 . product highlights 1. 2 s co n v ersio n tim e an d lo w p o w e r co n s um p t ion. 2. i 2 c-co m p a t ib le s e r i al in t e r f ace wi th p i n-s e le c t ab le addr ess e s. t w o ad7992 v e rsion s al lo w f i v e ad7992 de vices to b e conn e c te d to t h e s a m e s e r i a l b u s. 3. the p a r t fe a t ur e s a u t o ma t i c sh ut do w n w h i l e n o t co n v er t i ng t o maximize p o w e r ef f i cien c y . c u r r en t co n s u m p t ion is 1 a max w h en in sh u t do wn mo de a t 3 v . 4. refer e n c e can b e dr i v e n u p to t h e p o w e r su p p ly . 5. o u t-o f -r a n ge i ndic a to r t h a t can b e s o f t wa r e dis a b l e d o r ena b le d. 6. on e - sh o t and a u t o ma tic con v e r sio n ra t e s. 7. reg i sters sto r e mini m u m an d max i m u m con v ersio n re su lt s . tab l e 1. related prod ucts part number no. of bits no. of channels package a d 7 9 9 8 1 2 8 2 0 - t s s o p a d 7 9 9 4 1 2 4 1 6 - t s s o p a d 7 9 9 7 1 0 8 2 0 - t s s o p a d 7 9 9 3 1 0 4 1 6 - t s s o p
ad7992 rev. 0 | page 2 of 28 table of contents specifications ..................................................................................... 3 i 2 c timing specifications ................................................................ 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and pin function descriptions ...................... 8 ter mi nolo g y ...................................................................................... 9 typical performance characteristics ........................................... 10 circuit information ........................................................................ 13 converter operation .................................................................. 13 typical connection diagram ................................................... 14 analog input ............................................................................... 14 internal register structure ............................................................ 16 address pointer register ........................................................... 16 configuration register .............................................................. 17 conversion result register ....................................................... 18 limit registers ............................................................................ 18 alert status register ................................................................... 19 cycle timer register .................................................................. 19 sample delay and bit trial delay ............................................. 19 serial interface ................................................................................ 20 serial bus address ...................................................................... 20 writing to the ad7992 .................................................................. 21 writing to the address pointer register for a subsequent read .............................................................................................. 21 writing a single byte of data to the alert status register, cycle register, or configuration register ............................... 21 writing two bytes of data to a limit register or hysteresis register ........................................................................................ 22 reading data from the ad7992 ................................................... 23 alert/busy pin .......................................................................... 24 smbus alert ............................................................................ 24 placing the ad7992-1 into high speed mode ....................... 24 the address select (as) pin ..................................................... 24 modes of operation ....................................................................... 25 mode 1using the convst pin ........................................... 25 mode 2 C command mode ....................................................... 26 mode 3automatic cycle mode ............................................. 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 1/05revision 0: initial version
ad7992 rev. 0 | page 3 of 28 specifications temperature range for b version is ?40c to +125c. unless otherwise noted, v dd = 2.7 v to 5.5 v; ref in = 2.5 v to v dd . for the ad7992-0, all specifications apply for f scl up to 400 khz; for the ad7992-1 all specifications apply for f scl up to 3.4 mhz. all specifications are for both single-channel mode and dual-channel mode, unless otherwise noted; t a = t min to t max . table 2. parameter b version unit test conditions/comments dynamic performance 1 f in = 10 khz sine wave for f scl from 1.7 mhz to 3.4 mhz f in = 1 khz sine wave for f scl up to 400 khz signal-to-noise + distortion (sinad) 2 70.5 db min signal-to-noise ratio (snr) 2 71 db min total harmonic distortion (thd) 2 C78 db max peak harmonic or spurious noise (sfdr) 2 C79 db max intermodulation distortion (imd) 2 fa = 10.1 khz, fb = 9.9 khz for f scl from 1.7 mhz to 3.4 mhz fa = 1.1 khz, fb = 0.9 khz for f scl up to 400 khz second-order terms C90 db typ third-order terms C90 db typ aperture delay 2 10 ns max aperture jitter 2 50 ps typ channel-to-channel isolation 2 ?90 db typ f in = 108 hz; see the terminology section full power bandwidth 2 11 mhz typ @ 3 db 2 mhz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 1 , 2 1 lsb max 0.2 lsb typ differential nonlinearity 1 , 2 +1/C0.9 lsb max guaranteed no missed codes to 12 bits 0.2 lsb typ offset error 2 4 lsb max mode 1 ( convst mode) 6 lsb max mode 2 (command mode) offset error match 2 1 lsb max dual-channel mode gain error 2 2 lsb max gain error match 2 1 lsb max dual-channel mode analog input input voltage range 0 to ref in v dc leakage current 1 a max input capacitance 30 pf typ reference input ref in input voltage range 1.2 to v dd v min/v max dc leakage current 1 a max input impedance 69 k? typ logic inputs (sda, scl) input high voltage, v inh 0.7 (v dd ) v min input low voltage, v inl 0.3 (v dd ) v max input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 3 10 pf max input hysteresis, v hyst 0.1 (v dd ) v min
ad7992 rev. 0 | page 4 of 28 parameter b version unit test conditions/comments logic inputs ( convst ) input high voltage, v inh 2.4 v min v dd = 5 v 2.0 v min v dd = 3 v input low voltage, v inl 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 3 10 pf max logic outputs (open drain) output low voltage, v ol 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma floating-state leakage current 1 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary conversion rate see the serial interface section conversion time 2 s typ throughput rate mode 1 (reading after the conversion) 5 ksps typ f scl = 100 khz 21 ksps typ f scl = 400 khz 121 ksps typ f scl = 3.4 mhz mode 2 5.5 ksps typ f scl = 100 khz 22 ksps typ f scl = 400 khz 147 ksps typ f scl = 3.4 mhz , 188 ksps typ @ 5 v power requirements v dd 2.7/5.5 v min/max i dd digital inputs = 0 v or v dd power-down mode, interface inactive 1/2 a max v dd = 3.3 v/5.5 v power-down mode, interface active 0.07/0.3 ma max v dd = 3.3 v/5.5 v, 400 khz f scl 0.3/0.6 ma max v dd = 3.3 v/5.5 v, 3.4 mhz f scl operating, interface inactive 0.06/0.1 ma max v dd = 3.3 v/5.5 v, 400 khz f scl 0.3/0.6 ma max v dd = 3.3 v/5.5 v, 3.4 mhz f scl operating, interface active 0.15/0.4 ma max v dd = 3.3 v/5.5 v, 400 khz f scl 0.6/1.1 ma max v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode1 0.7/1.4 ma typ v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 2 mode 3 (i 2 c inactive, t convert 32) 0.7/1.5 ma max v dd = 3.3 v/5.5 v power dissipation fully operational operating, interface active 0.495/2.2 mw max v dd = 3.3 v/5.5 v, 400 khz f scl 1.98/6.05 mw max v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 1 2.31/7.7 mw typ v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 2 power down, interface inactive 3.3/11 w max v dd = 3.3 v/5.5 v 1 maximum/minimum ac dynamic performance, inl and dnl specifications are typical specific ations when operating in mode 2 with i 2 c high speed mode scl frequencies. specifications outlined for mode 2 apply to mode 3 also. sample delay and bit trial delay enabled. 2 see the terminology section. 3 guaranteed by initial characterization.
ad7992 rev. 0 | page 5 of 28 i 2 c timing specifications guaranteed by initial characterization. all values measured with the input filtering enabled. c b refers to the capacitive load on the bus line. t r and t f measured between 0.3 v dd and 0.7 v dd . high speed mode timing specifications apply to the ad7992-1 only. standard and fast mode timing specifications apply to both th e ad7992-0 and the ad7992-1. see figure 2. unless otherwise noted, v dd = 2.7 v to 5.5 v; ref in = 2.5 v to v dd ; t a =t min to t max . table 3. limit at t min , t max parameter conditions min max unit description f scl standard mode 100 khz serial clock frequency fast mode 400 khz high speed mode c b = 100 pf max 3.4 mhz c b = 400 pf max 1.7 mhz t 1 standard mode 4 s t high , scl high time fast mode 0.6 s high speed mode c b = 100 pf max 60 ns c b = 400 pf max 120 ns t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s high speed mode c b = 100 pf max 160 ns c b = 400 pf max 320 ns t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns high speed mode 10 ns t 4 1 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s high speed mode c b = 100 pf max 0 70 2 ns c b = 400 pf max 0 150 ns t 5 standard mode 4.7 s t su;sta , setup time for a repeated start condition fast mode 0.6 s high speed mode 160 ns t 6 standard mode 4 s t hd;sta , hold time for a repe ated start condition fast mode 0.6 s high speed mode 160 ns t 7 standard mode 4.7 s t buf , bus free time between a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for stop condition fast mode 0.6 s high speed mode 160 ns t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf max 10 80 ns c b = 400 pf max 20 160 ns
ad7992 rev. 0 | page 6 of 2 8 limit at t min , t ma x p a r a m e t e r c o n d i t i o n s m i n m a x u n i t d e s c r i p t i o n t 10 standard mode 300 ns t fd a , fall time of sda signal fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf max 10 80 ns c b = 400 pf max 20 160 ns t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf max 10 40 ns c b = 400 pf max 20 80 ns t 11a standard mode 1000 ns t rcl1 , rise time of scl signal after a repeated star t condition and af ter an ackno wle dge bit fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf max 10 80 ns c b = 400 pf max 20 160 ns t 12 standard mode 300 ns t fc l , fall time of scl signal fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf max 10 40 ns c b = 400 pf max 20 80 ns t sp fast mod e 0 50 ns pulse wid t h of suppressed s p ike high speed mode 0 10 ns t power - up 1 s typ power-up time 1 a devi ce m u st pr o v i d e a da t a h o ld t i m e f o r sd a i n ord e r t o bri d g e t h e un de fi n e d r e gi on of t h e scl fa l l i n g e d ge. 2 for 3 v supp li es, t h e maximum hol d time with c b = 100 p f max is 100 ns ma x. p s s p t 6 t 4 t 1 t 3 t 5 t 8 t 2 t 11 t 12 t 6 scl sda t 7 t 9 t 10 s = start condition p = stop condition 03623-0-019 f i gure 2. t w o - wire s e r i a l in ter f ac e tim i ng d i agr a m
ad7992 rev. 0 | page 7 of 2 8 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. table 4. p a r a m e t e r r a t i n g v dd to gnd ? 0.3 v to 7 v analog input voltage to gnd ? 0.3 v to v dd + 0.3 v reference input voltage to gnd ? 0.3 v to v dd + 0.3 v digital input voltage to gnd ? 0.3 v to +7 v digital output v o ltage to gnd ? 0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating tem p erature range commercia l (b version) ? 40c to +125c storage temperature range ? 65c to +150 junction tempe r ature 150c 10-lead msop package ja thermal impedance 200c/w (msop ) jc thermal impedance 44c/ w (msop) pb/sn tempera ture, soldering reflow (10 sec to 30 sec) 240 (+0/ ? 5)c pb-free temper ature, soldering reflow 260 (+0)c e s d 1 . 5 k v 1 t r ansien t cur r en ts of up t o 100 m a do not cause scr la t c h-up . s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7992 rev. 0 | page 8 of 2 8 pin conf igura t ion and pi n function descriptions ad7992 top view 1 2 3 4 7 8 9 10 sda scl v dd agnd agnd 5 (not to scale) alert 6 as v in 1 v in 2/ref in 03263-0-002 convst f i g u re 3. a d 79 92 p i n conf ig ur at io n ta ble 5. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 2, 7 agnd analog ground. ground reference point for all circuitr y on the a d 7992. all analog input signals should be referred to this gnd voltage. 3 v dd power supply input. the v dd range for the ad79 92 is from 2.7 v to 5.5 v. 4 v in 2/ref in analog input 2/ voltage reference input. in singl e -chann el mode , this pin bec o m e s the reference voltage input; an externa l refer e nce sh ould be appli e d at this pi n. the external reference input range is 1.2 v to v dd . a 0.1 f and 1f capacit o r should be tie d between this pin and agnd . i f bit d6 is set to 1 in the configuration register, the ad7992 operates in single-channe l mode. in dual-channe l mode, d6 in the configuration register is 0; in this case, this pi n provides the second analog inp ut channel. the reference voltage for the ad7992 is taken from the power supply voltage i n dual-channe l mode. s ee the configuration register section an d table 10. 5 v in 1 analog input 1. single-ended analog in put channel. the input range is 0 v to ref in . 6 as logic input. add r ess sele ct inp ut that selects one of three i 2 c addresses for the ad7992, as shown in table 6. 1 convst logic input signal. convert start sign al. this i s an edge-triggered logic inp ut. the rising edge of this signal power s up the part. t h e power up time for the part is 1 s. the falling edge of convst places the trac k-a n d- hold into hold mode and initiates a conver sion . a powe r-up time of at least 1 s must be allo wed for the convst high pulse; oth e rwise, the co nv ersion re sult is i n valid ( s ee the m o d e s of opera tion section) . 8 a l e r t / b u s y digital output. selectable as an aler t or busy output function. when configur ed as an alert, this pin acts as an out-of-range indicator and, if enabl e d, becom e s active whe n the conver sion r e sult violates th e data high or data low register values. see the limit registers section. wh en c o nfigured as a busy output, this pin becom e s active when a c o nversi on is in p r ogress. o p en-d rain output. an ex ternal pull-up resistor is req u ired. 9 sda digital i/o. seria l bus bidirection a l data. open-dr ain output. an ex ternal pull -up r e sistor is re quire d . 10 scl digital input. serial bus clock. open-drain output. an ex ternal pull-up resistor is req u ired. table 6. i 2 c a d d r ess selection part number as pin i 2 c addr ess ad7992-0 gnd 010 0001 ad7992-0 v dd 010 0010 ad7992-1 gnd 010 0011 ad7992-1 v dd 010 0100 ad7992-x 1 float 010 0000 1 i f the as pin is left float ing on any of the ad7992 parts, t h e device address is 010 0000. this gives each ad7992 device thre e diff eren t addre s s opt i on s.
ad7992 rev. 0 | page 9 of 2 8 terminology si g n a l - t o - n o i s e a n d d i s t or t i on r a t i o ( s i n a d ) t h e me a s u r e d r a t i o of s i g n a l - t o - noi s e a n d d i s t or t i on a t t h e o u t p ut o f t h e a/ d co n v er t e r . the sig n al is t h e r m s a m pl i t u d e o f t h e fun d a m en tal . n o ise i s t h e s u m o f all n o nfun da m e n t al s i gnals u p t o half the s a m p lin g f r e q ue nc y (f s /2), excl udin g dc. th e ra t i o i s d e pen d e n t o n th e n u m b e r o f q u a n tiz a ti o n lev e ls i n t h e di gi t - i z a t i o n p r oce ss; th e m o r e lev e l s, th e smalle r th e q u a n tiz a ti o n n o is e. th e t h e o r e t i cal sig n al-t o - n o is e an d dist o r t i o n ra t i o fo r a n i d eal n- b i t co n v e r t e r wi t h a si n e wa v e in p u t i s gi v e n b y sig n al - to -( no i s e + dis t o r t i o n ) = (6.02 n + 1.76) db th us, t h e s i n a d is 74 db f o r a 12-b i t con v er t e r . t o t a l ha r m on i c d i s t or t i on ( t h d ) t h e r a t i o of t h e r m s su m of h a r m on i c s to t h e f u n d a me n t a l . f o r th e ad7992, i t is def i ned as 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 ) db ( + + + + = w h er e v 1 is t h e r m s a m pli t ude o f t h e f u ndam e n t al , and v 2 , v 3 , v 4 , v 5 , a nd v 6 a r e t h e r m s am pl i t u d es o f t h e s e c o n d t h r o ug h six t h ha r m o n ics . p e a k h a rmo n i c o r s p uri o us n o is e the ra t i o o f t h e r m s val u e o f t h e n e xt la rg es t co m p on e n t i n t h e ad c o u t p u t s p e c t r um (u p t o f s /2 a nd excl ud ing dc) to t h e r m s va l u e o f t h e f u ndame n t a l. t y p i c a l l y , t h e va l u e o f t h i s s p e c if i c a t ion is det e r m i n e d b y t h e la rgest ha r m o n ic in t h e sp e c t r um, b u t fo r ad cs w h er e t h e ha r m o n ic s a r e b u r i e d in t h e no is e f l o o r , i t is a noi s e p e a k . inte r m o d u l at i o n d i s t or t i on w i t h i n put s c o n s i s t i ng of s i ne w a ve s a t t w o f r e q u e nc i e s , f a a nd fb , an y ac t i ve de vic e wi t h no n l i n e a r i t i es cr e a tes di sto r t i o n p r o d uc ts a t s u m a nd dif f er en ce f r e q uen c ies o f mfa nf b , w h ere m, n = 0, 1, 2, 3, a nd s o o n . i n te r m o d u l a t io n disto r t i o n ter m s a r e th ose f o r whic h n e i t h e r m n o r n eq ual zer o . f o r exa m p l e , s e co nd-o r der te r m s i n cl ude (f a + fb) a n d (f a ? fb ) , wh il e thir d-o r der t e r m s in c l ude (2fa + fb), (2fa ? fb),(fa + 2fb), a nd (fa ? 2fb). the ad7992 is t e s t e d usin g t h e ccif s t anda r d wher e tw o in p u t f r e q uen c ies n e ar t h e to p e nd o f t h e in p u t b a ndwi d t h a r e us e d . i n t h i s cas e , t h e s e co nd-o r der te r m s a r e usua l l y dist an ce d i n f r e q uen c y f r o m t h e o r ig inal si ne wa v e s w h i l e t h e t h ir d-o r der t e r m s a r e us ual l y a t a f r eq uen c y c l os e t o the in p u t f r eq uen c ies. a s a r e su lt, t h e s e co nd- and t h i r d-o r der ter m s a r e sp e c if ie d s e p a r a tely . t h e ca lc u l a t io n o f i n ter m o d u l a t ion disto r t i o n is, li k e t h e thd sp e c if ica t ion, t h e ra t i o o f t h e r m s sum o f t h e indivi d u al di s t or t i o n p r o d uc ts to t h e r m s am pli t ude o f t h e s u m o f t h e f u ndam e n t als, exp r es s e d in db . c h a nne l-t o -c ha nn e l i s ola t i o n a me asur e o f t h e le vel o f cr osst a l k b e tw e e n channels, t a k e n b y a p p l y i n g a f u l l -s cal e sin e wa ve sig n al t o t h e u n s e lec t ed in p u t c h a nne ls, an d det e r m inin g h o w m u c h t h e 108 h z sig n al is a t t e n u a t ed i n t h e se l e c t ed c h a n n e l . th e sin e wa v e s i gn al a p p l i e d t o th e u n s e lec t e d c h a n ne ls is then va r i e d f r o m 1 kh z u p t o 2 mh z, e a c h t i m e det e r m inin g h o w m u ch t h e 108 h z sig n al in t h e s e le c t e d channe l is a t ten u a t e d . this f i gur e r e p r es en ts t h e w o rs t-cas e le ve l acr o s s al l c h a nne ls. ap e r t u r e d e l a y the m e as ur e d i n t e r v al b e tw e e n t h e s a m p li n g cl o c k s le adin g e d g e an d t h e p o in t a t w h ich t h e ad c t a k e s t h e s a m p le . a p e r tu r e j i tt e r the s a m p le -t o- s a m p le va r i a t io n i n t h e ef fe c t i v e p o in t i n t i me w h en t h e s a m p l e is t a k e n. fu l l - p o w e r b a n d w i d t h the i n pu t f r e q u e n c y a t w h ich t h e am pl i t u d e o f t h e re cons t r uc t e d f u ndam e n t al is r e d u ced b y 0.1 db o r 3 db f o r a f u l l -s cale in p u t. p o wer s u pply rej e c t i o n r a ti o ( p s rr) the ra t i o o f t h e p o w e r i n t h e a d c o u t p u t a t t h e f u l l -s cale fr e q u e n c y , f , t o th e p o w e r o f a 2 00 mv p-p sine wa v e a p p l ie d to t h e a d c v dd su p p ly of f r e q ue nc y f s : ps rr (db) = 10 log ( pf / pf s ) w h er e pf is th e p o w e r a t f r eq uen c y f in t h e ad c o u t p ut; pf s is th e po w e r a t f r eq ue n c y f s co u p led o n t o t h e ad c v dd su p p ly . inte g r a l n o n l i n e a r i t y the maxi m u m de v i a t io n f r o m a st ra ig h t l i n e p a ssin g t h r o ug h t h e end p o i n t s of t h e ad c t r a n s f er f u n c t i o n . the end p oin t s a r e z e r o scale , a po in t 1 l s b b e lo w th e f i r s t code tra n si ti o n , a n d fu ll s c ale , a p o i n t 1 ls b a b o v e t h e l a s t co de t r a n si t i o n . d i f f erenti a l n o n l i n e a r i ty the dif f er en ce b e tw e e n t h e m e as ur e d an d t h e i d e a l 1 ls b ch ange b e t w e e n an y t w o a d j a c e n t c o d e s i n t h e a d c . off s et err o r the devia t ion o f th e f i rs t co de t r a n si tio n (00 000) t o (00001) f r o m th e ide a ltha t is, a g nd + 1 l s b . off s et err o r ma t c h the dif f er en ce i n o f fs et er r o r b e tw e e n an y tw o cha nne ls. ga in e r r o r the devia t ion o f th e las t c o de tr a n si tion (111110) t o (111111) f r o m t h e ideal (tha t is, ref in ? 1 l s b) a f t e r th e o f fse t e r r o r h a s been a d j u s t ed o u t . ga in e r r o r m a t c h the dif f er en ce i n ga in er r o r b e t w e e n an y t w o cha nne ls.
ad7992 rev. 0 | page 10 of 28 typical perf orm ance cha r acte ristics ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 s i nad (db) 20 40 06 0 60 62 64 66 68 70 72 74 76 1 1 0 100 input frequency khz s i nad (db) v dd = 5.5v v dd = 5.0v v dd = 4.5v v dd = 2.7v v dd = 3.0v v dd = 3.3v v ref = v dd 03263-0-020 frequency (khz) 03263-0-024 f s = 121ksps f scl = 3.4mhz f in = 10khz snr = 71.84db sinad = 71.68db thd = ? 86.18db sfdr = ? 88.70db f i g u re 4. d y na mi c p e r f o r m a nce w i t h 5 v su p p ly and 2. 5 v r e f e r e nce , 12 1 k s ps, m o de 1, sing l e - c han n e l m o de ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (khz) s i nad (db) snr = 73.23db sinad = 73.10db thd = ? 88.59db sfdr = ? 90.46db f s = 121ksps f scl = 3.4mhz f in = 10khz 06 0 10 20 30 40 50 03263-0-021 f i g u re 5. d y na mi c p e r f o r m a nce w i t h 5.5 v sup p l y a n d 5. 5 v r e f e r e n c e , 12 1 ksp s , m o de 1, d u a l - c hann el m o d e 20 40 70 80 90 100 p s rr (db) 10 1000 supply-ripple frequency (khz) 03263-0-025 100 v dd = 3v v dd = 5v 50 30 60 v dd = 3v/5v 20 0m v p - p s i n e w a v e on v dd 2nf capacitor on v dd f i g u re 6. psr r v s . sup p ly-r ip p l e f r equ e nc y , sing le - c h a nn el m o de o n ly f i g u re 7. sina d v s . a n al og input f r equ e nc y f o r v a ri ous su p p ly v o lt ag es at 13 6 k s ps w i t h 3.4 m h z f scl ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 inl e rror (ls b ) 20 00 1 500 5 0 0 1 000 0 2 5 0 0 300 0 350 0 4 000 code 03263-0-026 fi g u r e 8 . t y p i c a l i n l , v dd = 5.5 v , r e f e renc e = 2.5 v , m o d e 1, 3.4 m h z f scl , 121 ksp s ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 dnl e rror (ls b ) 2000 150 0 500 100 0 0 2500 3 000 3500 4000 code 03263-0-027 fi g u r e 9 . t y p i c a l d n l , v dd = 5. 5 v , r e f e r e nc e = 2.5 v m o d e 1, 3.4 m h z f scl , 121 ksp s
ad7992 rev. 0 | page 11 of 28 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 inl e rror (ls b ) 2 000 15 00 500 100 0 0 2500 300 0 3 5 0 0 4 000 code 03263-0-016 f i g u re 10. t y pic a l i n l, v dd = 2. 7 v , r e f e r e nc e = 2.5 v , m o d e 1, 3.4 m h z f scl , 121 ksp s ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 dnl e rror (ls b ) 2 000 15 00 5 0 0 100 0 0 2500 300 0 3 5 0 0 4000 code 03263-0-017 f i g u re 11. t y pic a l d n l, v dd = 2. 7 v , r e f e r e nc e = 2.5 v , m o d e 1, 3.4 m h z f scl , 121 ksp s inl e rror (ls b ) reference voltage (v) 03263-0-030 ? 1.0 ? 0.8 -0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 positive inl negative inl f i gure 1 2 . change in inl vs . re fe r e nc e v o l t a g e , v dd = 5 v , m o de 1, 12 1 k s ps dnl e rror (ls b ) reference voltage (v) 03263-0-031 ? 1.0 ? 0.8 -0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 positive dnl negative dnl f i gure 1 3 . change in dnl vs . reference v o l t a g e , v dd = 5 v , mo de 1 , 12 1 ksp s s u p p l y curre nt (ma) supply voltage (v) 03263-0-032 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 2.7 3.2 3.7 4.2 4.7 5.2 +25 c +85 c ?4 0 c f i gure 14. sh u t do w n c u r r ent vs. sup p l y v o l t a g e , C4 0c, +2 5 c, a n d +85 c s u p p l y curre nt (ma) scl frequency (khz) 03263-0-033 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 100 600 1100 1600 2100 2600 3100 mode 1 vdd = 5v mode 1 vdd = 3v mode 2 vdd = 5v mode 2 vdd = 3v f i gure 15. a v er ag e sup p ly cu rrent v s . i 2 c bus r a t e f o r v dd = 3 v a n d 5 v
ad7992 rev. 0 | page 12 of 28 03263-0-034 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 12.0 1.200 2.048 2.500 2.700 3.000 3.300 4.096 4.500 5.000 reference voltage (v) enob ( b its) 68 69 70 71 72 73 74 s i nad (db) enob v dd = 3v enob v dd = 5v sinad v dd = 3v sinad v dd = 5v f i g u re 16. e n ob/si n a d v s . r e f e r e n c e v o lt ag e , m o de 1, 1 21 k s ps
ad7992 rev. 0 | page 13 of 28 circuit i n forma t ion the ad7992 is a lo w p o w e r , 12 -b i t , sing le-s u p pl y , 2-c h a n ne l a n alog-t o-dig i t a l co n v er t e r (ad c ). th e p a r t can b e o p era t e d f r o m a 2.7 v t o 5.5 v s u p p l y . the ad7992 p r o v ides t h e us er wi th a 2-c h a n nel m u l t i p lexer , a n o n -chi p t r ack-and- h o ld , an ad c, an o n -chi p os ci l l a t o r , in ter n a l da t a r e g i sters, an d an i 2 c - c o m p a t i b l e se ri al in t e rf a c e , al l h o us e d i n a 10-le ad mso p p a cka g e t h a t o f fers t h e us er co n s idera b le s p ace-s a v i n g ad van t a g es o v er al t e r n a t i v e s o l u t i o n s. the ad7992 r e q u ir es a n ext e r n al r e f e r e n c e in t h e ra n g e o f 1.2 v to v dd . the ad7992 n o r m al l y r e ma in s in a p o w e r - do wn s t a t e while n o t co n v er t i ng. w h en s u p p l i es a r e f i rs t a p pl ie d , t h e p a r t co m e s u p in a p o w e r - do w n st a t e . p o w e r - up is ini t i a t e d p r i o r t o a co n- versio n, an d t h e de vice r e t u r n s to p o w e r - d o w n u p o n co m p let i o n o f t h e con v ersion. c o n v ersio n s can b e ini t ia t e d on th e ad7992 b y p u lsin g the co n v s t sig n al , usin g a n a u t o ma tic c y cle in ter v a l mo de o r a co mmand m o de w h er e wa k e - u p an d a co n v ersio n o c c u r d u r i n g a wr i t e addr ess f u n c t i o n (s e e t h e m o des o f o p er a t io n s e c t io n). o n co m p let i o n o f a co n v ersion, th e ad7992 a g ain en t e rs p o w e r - do wn m o de. this a u t o ma tic p o w e r - do wn fe a t ur e a l lo ws p o wer s a v i n g b e tw e e n con v ersio n s. this m e a n s an y r e ad o r wr i t e o p era t io n s acr o ss t h e i 2 c in t e r f ace ca n o c c u r w h i l e t h e de vic e is i n p o w e r - do wn. c o nverter oper a t ion the ad7992 is a s u cces si ve a p p r o x ima t ion, a n a l og-t o-dig i tal c o n v e r t e r ba sed a r o u n d a ca pa ci ti v e d a c . f i g u r e 1 7 a n d f i gur e 18 sh o w sim p lif i e d s c h e ma tics o f t h e ad c d u r i n g i t s acq u isi t ion an d co n v ersio n p h as es, r e s p ec ti ve l y . f i gur e 17 sh o w s t h e ad c d u r i ng i t s ac q u isi t ion phas e . sw2 is clos e d an d s w 1 is i n po s i ti o n a , th e c o m p a r a t o r i s he ld in a ba lance d con d i t ion, a nd t h e s a m p ling ca p a ci t o r acquir es t h e sig n al o n v in . capacitive dac v in comparator control logic sw1 a b sw2 ag nd 03473-0-018 f i g u re 17. a d c ac quis it i o n p h as e w h en t h e ad c s t a r ts a con v ersio n , as sh o w n i n f i gur e 18, sw2 o p e n s an d sw1 m o v e s t o p o si tio n b , ca us in g t h e co m p a r a t o r t o b e co m e u n bal a nced . the in p u t is dis c o n n e c t ed o n ce t h e co n v ersio n b e g i n s . the co n t r o l log i c a nd t h e c a p a ci t i ve d a c a r e us e d to add an d sub t r a c t f i xe d am o u n t s o f cha r ge f r o m t h e s a m p l i ng c a p a c i tor to b r i n g t h e c o m p ar a t or b a ck i n to a b a l a nc e d c o nd i t i o n . w h e n t h e c o m p ar a t or i s re b a l a nc e d , t h e co n v ersio n is com p let e . th e con t r o l log i c g e n e ra t e s t h e ad c output c o d e . f i g u re 1 9 show s t h e a d c t r ans f e r f u nc t i on . v in comparator control logic sw1 a b sw2 a gn d capacitive dac 03473-0-019 f i g u re 18. a d c co nvers i on p h as e adc transfer function the o u t p u t co din g o f th e ad79 92 is s t ra ig h t b i na r y . th e desig n e d co de t r a n si tio n s o c c u r a t s u cces s i v e in t e g e r ls b va l u es (i .e ., 1 ls b , 2 ls b , a nd s o on). th e ls b size f o r th e ad7992 is ref in /4096. f i g u r e 19 s h o w s t h e idea l tra n sf er c h a r ac t e r i s t ic f o r th e ad7992. 000 ... 000 adc code an alog input 0v to ref in 111...111 000 ... 001 000 ... 010 111 ... 110 111 ... 000 011...111 agnd + 1lsb +ref in ? 1lsb ad7992 1lsb = ref in /4096 03263-0-003 f i gur e 1 9 . ad79 92 t r ansfe r cha r a c te risti c
ad7992 rev. 0 | page 14 of 28 t y p i c a l c o nnec t i o n di a g r a m f i gur e 21 sh o w s th e typ i cal co nn ec tion dia g ram f o r th e ad7992. i n f i g u r e 21, th e addr es s s e lec t p i n (as) is tied t o v dd ; h o wev e r as can als o be tie d t o a g nd o r lef t f l o a tin g , al lo wing th e us er t o s e lec t u p t o f i v e ad7 992 de vices on t h e s a me s e r i al b u s. an ext e r n a l r e f e r e n c e m u s t be a p p l ie d t o t h e ad7992. this r e f e r e n c e c a n b e in t h e ra ng e o f 1.2 v t o v dd . a p r e c isio n r e f e r e n c e lik e t h e ref 19x fa mily , ad r03, o r ad r381 ca n be us ed t o s u p p l y t h e r e f e r e n c e v o l t a g e t o t h e ad c. th e ad7992 ca n b e co nf igure d to b e a si n g le -cha n n el de vi ce wi t h t h e r e fer e n c e v o l t a g e a p plie d t o t h e v in 2/ref in p i n. the ad7992 ca n a l s o b e co nf igur e d as a d u a l -cha n n el de vi ce w h er e t h e r e fer e n c e v o l t a g e is t a k e n f r o m t h e s u p p l y v o l t ag e v dd , a nd t h e v in 2/ref in tak e s o n i t s a n alog in p u t f u n c tion,v in 2. s d a and scl fo r m t h e 2- wir e i 2 c/s m b u s-com p a t i b le in t e r f ace . e x t e r n al p u l l -u p r e sis t ers a r e r e q u ir e d fo r bo t h s d a and scl lin e s. the ad7992 -0 s u p p o r ts s t andar d a nd fast i 2 c in t e r f ac e m o des. the ad7992 -1 s u p p o r ts s t andar d , fas t , and hig h s p ee d i 2 c in t e r f ace m o des . ther ef o r e , if o p era t in g t h e ad7992 in ei t h er s t anda r d o r fas t m o de , u p t o f i ve ad7992 de vic e s ca n be co nn ec t e d t o t h e b u s (3 ad7 992-0 a nd 2 ad7992-1 o r 3 ad7992-1 and 2 ad7992 -0). i n hig h s p e e d m o de , u p t o thr e e ad7992 -1 de vices ca n be co nn ec t e d t o the b u s. w a ke u p f r o m p o w e r - do wn p r io r t o a co n v ersio n is a p p r o x - ima t e l y 1 s, and co n v ersio n t i m e is a p p r o x im a t e l y 2 s. t h e ad7992 en t e rs s h u t do wn m o de a g a i n a f t e r each co n v ersio n , w h ich is us ef u l i n a p pli c a t io n s w h er e p o w e r con s um p t io n is a co n c er n. anal og input f i gur e 20 sh o w s a n eq uivalen t c i r c ui t o f t h e ad7992 a n alog in p u t s t r u c t ur e . the t w o dio d es, d1 a nd d2, p r o v ide es d p r o t ecti o n f o r th e a n alog i n p u ts. ca r e m u st b e tak e n t o e n s u r e tha t t h e analog in p u t sig n al do es n o t excee d t h e s u p p l y ra ils b y m o r e t h a n 3 00 mv . this c a us es t h es e dio d es t o b e com e f o r w a r d - b i ased a n d s t a r t co n d ucti n g curr e n t i n t o th e s u bs tra t e . th e s e dio d e s can co nd uc t a ma x i m u m c u r r en t o f 10 ma wi t h o u t c a usin g ir r e v e rsi b le dama ge t o t h e p a r t . v in d1 v dd d2 r1 c2 30pf c1 4pf conversion phase - switch open track phase - switch closed 03473-0-022 f i g u re 20. equiv a le nt a n al og input c i rcuit ca p a c i t o r c1 in f i gur e 20 is typ i cal l y abo u t 4 p f a n d ca n pr i m ar i l y b e att r ibu t e d to pi n c a p a c i t a nc e. r e s i s t or r 1 i s a l u m p e d com p on e n t ma de u p of t h e on r e sist ance ( r on ) o f a t r ack-and- h o l d sw i t ch, and a l s o t h e r on o f t h e in pu t m u l t i- p l exer . th e t o tal r e sis t o r is typ i c a l l y a b o u t 400 ?. c2, the ad c s a m p ling ca p a c i t o r , has a typ i cal ca p a ci tan c e o f 30 pf . v dd v in 1 gnd 5v supply ref 19x 1 f 0.1 f 10 f ad7992 0v to ref in input sda c/ p scl 2-wire serial interface convst alert v in 2/ref in r p r p r p set to required address as 03263-0-004 0.1 f f i gure 21. ad7992 t y pic a l conne c t ion d i ag r a m, sing le - c hann el m o d e , m o d e 1
ad7992 rev. 0 | page 15 of 28 f o r a c a p pl i c a t i o ns , re mov i ng h i g h f r e q u e nc y c o m p o n e n t s f r om t h e ana l o g in p u t sig n a l is r e co mmende d b y us e o f a n rc b a nd - p a s s f i l t er o n t h e r e levan t a n alog in p u t p i n. i n a p p l ica t io n s w h er e ha r m oni c dis t o r t i o n and sig n al-t o- n o is e ra t i o a r e cr i t ic al, t h e analog in p u t sh o u ld b e dr i v en f r o m a lo w i m p e dan c e s o ur ce . l a rge s o ur ce im p e dan c e s sig n if ican t l y a f fe c t t h e ac p e r f o r ma n c e o f t h e ad c. this ma y ne ces s i t a t e t h e us e o f a n in p u t b u f f er a m plif ier . the ch o i ce o f t h e o p am p is a f u n c t i o n o f t h e p a r t ic u l a r a p plic a t ion. w h en n o am pli f ier is us e d t o dr i v e t h e a n alog i n p u t , t h e s o ur ce im p e dan c e sh ou ld b e l i m i te d to lo w va l u es. t h e max i m u m s o ur ce i m p e dance dep e n d s o n t h e am o u n t o f tot a l ha r m onic d i s t o r ti o n (t hd ) th a t ca n be t o le ra t e d . t h d in cr ea se s a s th e s o ur ce i m p e d a nce i n cr e a s e s, and p e r f o r ma n c e deg r ades. fi g u r e 2 2 s h ow s t h e t h d v s . t h e a n a l o g i n p u t s i g n a l f r e q u e n c y when usin g s u p p l y v o l t a g es o f 3 v 10% an d 5 v 10%. fi g u r e 2 3 s h ow s t h e t h d v s . t h e a n a l o g i n p u t s i g n a l f r e q u e n c y fo r dif f er en t s o ur ce im p e dan c es. ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 10 100 input frequency (khz) thd (db) 1 v ref = 2.5v v dd = 2.7v v dd = 3.0v v dd = 3.3v v dd = 5.5v v dd = 5.0v v dd = 4.5v 03263-0-022 f i g u re 22. th d v s . a n al og input f r equ e nc y f o r v a ri ous sup p ly v o lt ag es, f s = 136 ksp s , mo de 1 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 1 1 0 100 input frequency (khz) thd (db) v dd = 5.5v v ref = 2.5v r source = 1k ? r source = 100 ? r source = 0 ? r source = 10 ? 03263-0-023 r source = 50 ? f i g u re 23. th d v s . a n al og input f r equ e nc y f o r v a ri ous s o u r c e impedanc es for v dd = 5. 5 v , 13 6 k s p s , m o d e 1
ad7992 rev. 0 | page 16 of 28 internal register structure the ad7992 con t a i n s 11 in t e r n al r e g i s t ers (s ee f i gur e 24) tha t a r e us e d t o s t o r e co n v ersion r e su l t s, hig h an d lo w co n v ersion limi ts, an d info r m a t io n to co nf i g ur e a nd co n t r o l t h e de vi ce. ther e a r e t e n da t a r e g i st ers an d o n e addr es s p o i n t e r r e g i s t er . 03263-0-005 conversion result register alert status register cycle timer register hysteresis register ch1 hysteresis register ch2 configuration register data low register ch1 data low register ch2 data high register ch2 data high register ch1 address pointer register serial bus i nterface sda scl d a t a f i gur e 2 4 . ad79 92 re gi st e r str u ctur e e a c h da t a r e g i ster has a n addr ess tha t t h e addr es s p o in t e r r e g i s t er p o in ts to wh en co mm u n ica t in g wi t h i t . the con v ersio n re su l t re g i ste r is t h e on ly d a t a re g i ste r t h a t is re a d -on l y . address pointer register b e ca us e i t is t h e r e g i s t er t o w h ich t h e f i rs t da t a b y t e o f e v er y wr i t e o p era t io n is wr i t t e n a u t o ma t i c a l l y , t h e addr es s p o in t e r r e g i s t er do es n o t ha v e and do es n o t r e q u ir e a n addr es s. th e addr es s p o in t e r r e g i s t er is a n 8- b i t r e g i s t er i n w h ich t h e 4 l s bs a r e us e d as p o i n t e r b i t s t o s t o r e a n addr es s t h a t p o in ts t o o n e o f th e ad7992 s d a ta r e g i st ers. the 4 ms bs a r e us ed as co mmand b i ts w h e n o p era t in g i n m o de 2 (s e e t h e m o des o f o p era t io n s e c t io n). th e f i rs t b y te fol l o w ing e a ch wr i t e addr es s is t h e addr es s o f on e of t h e da t a reg i s t ers, w h ich is s t or e d in t h e addr ess p o in ter r e g i ster a nd s e le c t s t h e da t a r e g i ster to w h ich sub s e q u e n t da t a b y te s are w r it te n. o n ly t h e 4 l s b s of t h i s r e g i s t er a r e us e d t o s e le c t a da t a r e g i s t er . o n p o w e r - u p , t h e addr ess p o in ter r e g i ster co n t ains a l l 0s, p o i n t i ng to t h e c o n v e r s i on re su lt re g i ste r . tab l e 7. add r ess poin ter register c 4 c 3 c 2 c 1 p 3 p 2 p 1 p 0 0 0 0 0 register s e l e c t table 8. ad79 92 register addresses p 3 p 2 p 1 p 0 r e g i s t e r s 0 0 0 0 conversi on resu lt register (read) 0 0 0 1 alert status register (read/write) 0 0 1 0 configuration register (read/wr ite) 0 0 1 1 cycle timer register (read/write) 0 1 0 0 data low register ch1 (read/write) 0 1 0 1 data high register ch1 (read/write) 0 1 1 0 hysteresis regist er ch1 (read/write) 0 1 1 1 data low register ch2 (read/write) 1 0 0 0 data high register ch2 (read/write) 1 0 0 1 hysteresis regist er ch2 (read/write)
ad7992 rev. 0 | page 17 of 28 configuration register the configuration register is a 8-bit, read/write register that is used to set the operating modes of the ad7992. the msb of th e register is unused and is a dont care bit. the bit functions of the configuration register are outlined in table 9. a single-byte write is necessary when writing to the configuration register. table 9. configuration register bit function descriptions and default settings at power-up d7 d6 d5 d4 d3 d2 d1 d0 dontc single/dual ch2 ch1 fltr alert en busy/alert alert/busy polarity 0 0 0 0 1 0 0 0 bit mnemonic comment d7 dontc dont care bit. d6 single/dual the value written to this bit dete rmines the functionality of the v in 2/ref in pin and the reference source for the conversions. when this bit is 1, the pin takes on its reference input function, ref in , making the ad7992 a single- channel part with the reference being taken from the ref in pin. however, when only channel 1 is selected for a conversion, the reference can also be taken from the supply voltage by setting d6 to 0. when this bit is a 0, the v in 2/ref in pin becomes a second analog input pin, v in 2, making the ad7992 a dual-channel part with the reference being taken from the supply voltage. see table 10. d5, d4 ch2, ch1 these two channel address bits select which analog input chan nel is to be converted. a 1 in any of bits d5 or d4 selects a channel for conversion. if more than one channel bit is set (with d6 = 0), the alternating channel sequence is used. table 10 shows how these two channel address bits are decoded. if d5 is selected, the part operates in dual-channel mode, with the reference for th e adc being taken from the supply voltage (d6 set to 0 for dual-channel mode). d3 fltr the value written to this bit of the control register determines whether the filtering on sda and scl is enabled or is bypassed. if this bit is a 1, th e the filtering is enabled; if it is a 0, the filtering is bypassed. d2 alert en the hardware alert function is en abled if this bit is set to 1 and disabled if this bit is se t to 0. this bit is used in conjunction with the busy/alert bit to determine if the alert/busy pin ac ts as an alert or a busy output (see table 11). d1 busy/alert this bit is used in conjunction with the alert en bit to determine if th e alert/busy pin acts as an alert or busy output (see table 11), and if configured as an alert output pin, if it is to be reset. d0 busy/alert polarity this bit determines the active polarity of the alert/busy pin regardless of wh ether it is configured as an alert or busy output. it is active low if this bit is set to 0 and active high if set to 1. table 10. channel and reference selection d6 single/dual d5 ch2 d4 ch1 analog input channel 0 0 0 no conversion 0 0 1 convert on v in 1 (reference from v dd ) 1 0 1 convert on v in 1 (reference from ref in ) 0 1 0 convert on v in 2 (reference from v dd ) 0 1 1 sequence between channel 1 and channel 2, beginning with channel 1 (reference from v dd ) table 11. alert/busy function d2 d1 alert/busy pin configuration 0 0 pin does not provide any interrupt signal. 0 1 pin configured as a busy output. 1 0 pin configured as an alert output. 1 1 resets the alert output pin, the alert_ flag bit in the conversion result re gister, and the entire alert status register (if any is active). if 1/1 is written to bits d2/d 1 in the configuration register to reset the alert pin, the alert_flag bit, and the alert status register, the contents of the configuration register read 1/0 for d2/d1, respectively, if read back.
ad7992 rev. 0 | page 18 of 28 conversion result register the conversion result register is a 16-bit, read-only register that stores the conversion result from the adc in straight binary format. a 2-byte read is needed to read data from this register. table 12 shows the contents of the first byte to be read from the ad7992, and table 13 shows the contents of the second byte. table 12. conversion value register (first read) d15 d14 d13 d12 d11 d10 d9 d8 alert_flag zero zero ch id0 msb b10 b9 b8 table 13. conversion value register (second read) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 the ad7992 conversion result consists of an alert_flag bit, two leading zeros, a channel identifier bit, and the 12-bit data result. the alert_flag bit indicates whether the conversion result being read or any other channel result has violated the limit registers associated with it. if an alert occurs, the master may wish to read the alert status register to obtain more informa- tion on where the alert occurred if the alert_flag bit is set. the alert_flag bit is followed by two leading zeros and a channel identifier bit that indicate to which channel the con- version result corresponds. when this bit is 0, the conversion result corresponds to v in 1, and when it is 1, the conversion result corresponds to v in 2. these, in turn, are followed by the 12-bit conversion result, msb first. limit registers the ad7992 has two pairs of limit registers. each pair stores high and low conversion limits for both analog input channels. each pair of limit registers has one associated hysteresis register. all 6 registers are 16 bits wide; only the 12 lsbs of the registers are used. on power-up, the contents of the data high register for each channel are full scale, while the contents of the data low registers are zero scale by default. the limit registers can be used to monitor the conversion results on one or both channels. the ad7992 signals an alert (in either hardware or software or both, depending on the configuration) if the result moves outside the upper or lower limit set by the user. data high register ch1/ch2 the data high register for a channel is a 16-bit, read/write register; only the 12 lsbs of each register are used. this register stores the upper limit that activates the alert output and/or the alert_flag bit in the conversion result register. if the value in the conversion result register is greater than the value in the data high register, an alert occurs. when the conversion result returns to a value at least n lsb below the data high register value, the alert output pin and alert_flag bit are reset. the value of n is taken from the 12-bit hysteresis register associated with that channel. the alert pin can also be reset by writing to bits d2 and d1 in the configuration register. table 14. ad7992 data high register (first read/write) d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 b11 b10 b9 b8 table 15. ad7992 data high register (second read/write) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 data low register ch1/ch2 the data low register for each channel is a 16-bit read/write register; only the 12 lsb of each register are used. the register stores the lower limit that activates the alert output and/or the alert_flag bit in the conversion result register. if the value in the conversion result register is less than the value in the data low register, an alert occurs. when the conversion result returns to a value at least n lsb above the data low register value, the alert output pin and alert_flag bit are reset. the value of n is taken from the hysteresis register associated with that channel. the alert output pin can also be reset by writing to bits d2 and d1 in the configuration register. table 16. data low register (first read/write) d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 b11 b10 b9 b8 table 17. data low register (second read/write) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 hysteresis register (ch1/ch2) each hysteresis register is a 16-bit read/write register; only the 12 lsbs of the register are used. the hysteresis register stores the hysteresis value, n, when using the limit registers. each pair of limit registers has a dedicated hysteresis register. the hysteresis value determines the reset point for the alert pin/alert_flag if a violation of the limits has occurred. for example, if a hysteresis value of 8 lsb is required on the upper and lower limits of channel 1, the 16 bit word, 0000 0000 0000 1000, should be written to the hysteresis register of ch1 (see table 8 for the address of this register). on power-up, the hysteresis registers contain a value of 8 lsb. if a different hysteresis value is required, that value must be written to the hysteresis register for the channel in question. table 18. hysteresis register (first read/write) d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 b11 b10 b9 b8 table 19. hysteresis register (second read/write) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0
ad7992 rev. 0 | page 19 of 28 using the limit registers to store min/max conversion results if full scalethat is, all 1sis written to the hysteresis register for a particular channel, the data high and data low registers for that channel no longer act as limit registers as previously described, but instead act as storage registers for the maximum and minimum conversion results returned from conversions on a channel over any given period of time. this function is useful in applications where the widest span of actual conversion results is required rather than us ing the alert to signal that an intervention is necessaryfor example, when monitoring temperature extremes during refrigerated goods transportation. note that on power-up, the contents of the data high register for each channel are full scale, while the contents of the data low registers are zero scale by default. therefore, min- imum and maximum conversion values being stored in this way are lost if power is removed or cycled. alert status register the alert status register is an 8-bit read/write register that provides information on an alert event. if a conversion results in activating the alert pin or alert_flag bit in the conversion result register (see the limit registers section) the alert status register may be read to gain further information. it contains two status bits per channel, one corresponding to each of the data high and data low limits. the bit with a status of 1 shows where the violation occurredthat is, on which channeland whether the violation occurred on the upper or lower limit. if a second alert event occurs on the other channel between receiving the first alert and interrogating the alert status register, the corresponding bit for that alert event is also set. the entire contents of the alert status register can be cleared by writing 1,1 to bits d2 and d1 in the configuration register, as shown in table 11. this can also be achieved by writing all 1s to the alert status register itself. thus, if the alert status register is addressed for a write operation, which is all 1s, the contents of the alert status register are cleared or reset to all 0s. table 20. alert status register d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 ch2 hi ch2 lo ch1 hi ch1 lo table 21. alert status register bit function descriptions bit mnemonic comment d0 ch1lo violation of data low limit on channel 1 if bit is set to 1, no violation if bit is set to 0. d1 ch1hi violation of data high limit on channel 1 if bit is set to 1, no violation if bit is set to 0. d2 ch2lo violation of data low limit on channel 2 if bit is set to 1, no violation if bit is set to 0. d3 ch2hi violation of data high limit on channel 2 if bit is set to 1, no violation if bit is set to 0. cycle timer register the cycle timer register is an 8-bit read/write register that stores the conversion interval value for the automatic cycle mode of the ad7992 (see the modes of operation section). the 5 msbs of the cycle timer register are unused and should contain 0s at all times (see the sample delay and bit trial delay section). on power-up, the cycle timer register contains all 0s, thus disabling automatic cycle operation of the ad7992. to enable automatic cycle mode, the user must write to the cycle timer register, selecting the required conversion interval. table 22 shows the structure of the cycle timer register, while table 23 shows how the bits in this register are decoded to provide various automatic sampling intervals. table 22. cycle timer register and defaults at power-up d7 d6 d5 d4 d3 d2 d1 d0 sample delay bit trial delay 0 0 0 cyc bit 2 cyc bit 1 cyc bit 0 0 0 0 0 0 0 0 0 table 23. cycle timer intervals cyc reg value conversion interval d2 d1 d0 (t convert =conversion time of adc ) 0 0 0 mode not selected 0 0 1 t convert 32 0 1 0 t convert 64 0 1 1 t convert 128 1 0 0 t convert 256 1 0 1 t convert 512 1 1 0 t convert 1024 1 1 1 t convert 2048 sample delay and bit trial delay it is recommended that no i 2 c bus activity occurs when a conversion is taking place. however, this may not be possible, for example, when operating in mode 2 or the automatic cycle mode. in order to maintain the performance of the adc in such cases, bits d7 and d6 in the cycle timer register are used to delay critical sample intervals and bit trials from occurring while there is activity on the i 2 c bus. this may have the effect of increasing the conversion time. when bits d7 and d6 are both 0, the bit trial and sample interval delaying mechanism are implemented. the default setting of d7 and d6 is 0. if bit trial delays extend longer than 1 s, the conversion terminates. when d7 is 0, the sampling instant delay is implemented. when d6 is 0, the bit trial delay is implemented. to turn off both the sample delay and bit trial delay, set d7 and d6 to 1.
ad7992 rev. 0 | page 20 of 28 serial interface control of the ad7992 is carried out via the i 2 c-compatible serial bus. the ad7992 is connected to this bus as a slave device under the control of a master device, such as the processor. serial bus address like all i 2 c-compatible devices, the ad7992 has a 7-bit serial address. the 3 msbs of this address for the ad7992 are set to 010. the device comes in two versions, the ad7992-0 and the ad7992-1. the two versions have three different i 2 c addresses available, which are selected by either tying the address select pin, as, to agnd or v dd , or by letting the pin float (refer to table 6). by giving different addresses for the two versions, up to five ad7992 devices can be connected to a single serial bus, or the addresses can be set to avoid conflicts with other devices on the bus. the serial bus protocol operates as follows. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line sda, while the serial clock line, scl, remains high. this indicates that an address/data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit that determines the direction of the data transferthat is, whether data is written to or read from the slave device. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is a 0, the master writes to the slave device. if the r/ w bit is a 1, the master reads from the slave device. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the receiver of data. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device pulls the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.
ad7992 rev. 0 | page 21 of 28 writing to the ad7992 d e p e nding o n t h e r e g i st er b e ing wr i t t e n t o , t h e r e a r e t h r e e dif f er en t wr i t es f o r th e ad7992. writing t o the addre ss pointer register for a subsequent read i n o r der t o r e ad f r o m a p a r t ic u l a r r e g i s t er , t h e addr es s p o in t e r r e g i s t er m u s t f i rs t co n t ain t h e addr es s o f t h a t r e g i s t er . i f i t do es n o t , t h e co r r e c t addr ess m u st b e wr i t te n to t h e a ddr ess p o in ter r e g i s t er b y p e r f o r min g a si n g le -b yte wr i t e op era t io n, as sh o w n in f i gur e 25. the wr i t e o p er a t ion co n s is ts o f t h e s e r i al b u s addr ess fol l o w e d b y t h e ad dr ess p o in ter b y te. n o da t a is wr i t t e n t o an y o f t h e da t a reg i s t ers. a r e ad o p era t io n ca n b e subs e q u e n t ly p e r f or me d to re ad t h e re g i ste r of i n te re st . writing a s i ngle b y te of d a t a t o the alert st a t us register, cy cl e register, or c o nfigur a t ion regis t er the aler t s t a t us r e g i s t er , c y cle r e g i s t er , a nd co nf i g ura t io n r e g i s t er a r e al l 8 - b i t r e g i s t ers, s o o n l y o n e b y t e of da t a c a n b e w r it te n to e a c h . w r i t i n g a s i ng l e b y te of da t a to one of t h e s e r e g i s t ers co n s is t s o f t h e s e r i a l b u s wr i t e addr es s , t h e ch os e n da t a r e g i s t er addr es s wr i t t e n t o t h e addr es s p o i n t e r r e g i s t er , fol l o w e d b y t h e d a t a b y te w r i tte n to t h e s e l e c t e d da t a re g i st e r . s e e f i gur e 26. sda start by master ack. by ad7992 ack. by ad7992 stop by master frame 1 serial bus address byte frame 2 address pointer register byte 19 1 9 c4 c3 c2 p2 p1 p0 a0 a1 a2 a3 0 0 scl 1 c1 p3 03263-0-006 r/w f i g u re 25. w r it ing t o t h e addres s p o int e r r e g i s t er to s e le c t a r e g i s t er f o r a su bs equent r e ad o p er at ion sda ac k. by ad7992 11 9 9 c4 c3 c2 p2 p1 p0 r/w a0 a1 a2 a3 0 0 scl 1 c1 p3 91 9 d7 d6 d5 d2 d1 d0 d4 d3 frame 3 data byte scl (continued) sda (continued) 03263-0-007 start by master ack. by ad7992 ack. by ad7992 stop by master frame 1 serial bus address byte frame 2 address pointer register byte f i gure 26. sing l e -b yte write s e quen c e
ad7992 rev. 0 | page 22 of 28 writing t w o b y tes o f d a t a t o a limit register or h y steresis register e a ch o f t h e li mi t r e g i s t ers an d h y s t er esis r e g i s t ers a r e 12-b i t r e g i s t ers, s o t w o b y t e s o f da t a a r e r e q u ir e d t o wr i t e a val u e t o an y on e of t h e m . w r it i n g t w o b y te s of d a t a to on e of t h e s e r e gi s t e r s co n s i s ts o f th e s e ri a l b u s w r i t e a d d r e s s, th e ch osen limi t r e g i s t er addr es s wr i t t e n t o t h e addr es s p o i n t e r r e g i s t er , f o l l ow e d by t w o d a t a by t e s w r i t t e n t o t h e s e l e c t e d d a t a r e g i s t e r . s e e f i gur e 27. i f the mas t er is wr i t e-addr es s i ng th e ad7992, i t ca n wr i t e t o more t h a n o n e re g i ste r w i t h out re - a d d re ss i n g t h e a d c . a f te r t h e f i rst wr i t e op era t ion has com p let e d fo r t h e f i rs t da t a r e g i s t e r , d u r i n g t h e n e xt b y t e , t h e mast er wr i t es t o t h e addr es s p o i n t e r b y t e t o s e le c t t h e n e xt da t a r e g i st er fo r a wr i t e op era t ion. this e l imina t es t h e ne e d t o r e -addr ess t h e de vi ce i n or der t o wr i t e t o anot he r d a t a re g i ste r . sda ack. by ad7992 ack. by ad7992 11 9 9 c4 c3 c2 p2 p1 p0 r/ w a0 a1 a2 a3 0 0 scl 1 c1 p3 1 99 d7 d6 d5 d2 d1 /0 d0 /0 d4 d3 ack. by ad7992 stop by master least significant data byte most significant data byte scl (continued) s da (continued) frame 1 serial bus address byte start by master frame 2 address pointer register 91 0 00 d10 d9 d8 0 d1 1 ack. by ad7992 03263-0-008 f i gure 27. t w o - b y te write s e quen c e
ad7992 rev. 0 | page 23 of 28 reading da t a from the ad7992 readin g da t a f r o m t h e ad7992 is a 1- o r 2-b y te o p era t io n. re adi n g b a ck t h e co n t e n ts o f t h e aler t s t a t us r e g i s t er , t h e co nf ig - ura t io n r e g i st er , o r t h e c y cle t i mer r e g i s t er is a si n g le- b yt e r e ad o p era t ion, as sho w n i n f i gur e 2 8 . this assu mes t h e p a r t ic u l a r r e g i s t er addr es s has p r e v io u s l y b e en s e t u p b y a sin g le -b yte wr i t e o p era t ion t o t h e addr es s p o in t e r r e g i s t er (s e e f i gur e 25). on ce t h e reg i s t er addr es s has b e e n s e t u p , an y n u m b e r o f r e ads ca n b e p e r f or me d f r om t h at p a r t i c u l ar re g i ste r w i t h out h a v i ng to wr i t e t o t h e addr es s p o in t e r r e g i s t er a g a i n. i f a r e ad f r o m a d i f f e r e n t re g i ste r i s re qu i r e d , t h e rel e v a n t re g i s t e r a d d r e s s h a s to b e wr i t te n to t h e ad dr ess p o i n ter r e g i ster , and a g ain an y n u mb e r of re a d s f r om t h i s re g i ste r m a y t h e n b e p e r f or me d. r e a d i n g d a ta fr o m th e c o n v e r s i o n r e s u l t r e gi s t e r , d a t a hi g h re g i ste r s , d a t a low r e g i s t ers, o r h y s t er esis r e g i s t ers is a 2- b y t e o p er a t ion, as sho w n i n f i gur e 2 9 . the s a m e r u les a p ply fo r a 2-b y te r e ad as a 1-b y te r e ad . w h en r e ad in g d a t a b a ck f r o m a r e g i st er , such as t h e co n v ersio n re su lt re g i ste r , i f more t h a n t w o re a d b y te s are s u pp l i e d , t h e s a m e o r n e w da ta is r e ad f r o m t h e ad7992 wi t h o u t the n eed to r e -addr e s s t h e de v i ce . this al lo ws t h e mast er to co n t in uo us l y re a d f r om a d a t a re g i ste r w i t h o u t h a v i ng to re - a d d r e s s t h e ad7992. s da 11 99 d7 d6 d5 d2 d1 d0 r/w a0 a1 a2 a3 0 1 sc l d4 d3 0 03263-0-009 start by master ack. by ad7992 no ack. by master stop by master frame 1 serial bus address byte frame 2 single data byte from ad7992 f i g u re 28. r e ad ing a s i ng le b y te of d a t a f r om a s e lec t ed r e g i s t er s d a 11 9 9 alert- flag zero d10 d9 d8 a0 a1 a2 a3 0 0 scl 1 d1 1 1 d7 d6 d5 d2 d1/0 d0/0 d4 d3 scl (continued) sda (continued) zero ch id r/w 03263-0-010 9 start by master ack. by ad7992 no ack. by master ack. by master stop b y master frame 1 serial bus address byte frame 2 most significant data byte from ad7992 frame 2 most significant data byte from ad7992 f i gur e 2 9 . rea d i n g t w o byt e s o f da t a f r om the c o n v er sion resul t regi ster
ad7992 rev. 0 | page 24 of 28 alert/busy pin the aler t / b u s y p i n ma y b e c o nf igur e d as a n aler t ou t p u t or b u s y output , a s sh ow n i n t a bl e 1 1 . smbus alert the ad7992 aler t o u t p u t is a n s m b u s in t e r r u p t line f o r de vices t h a t wan t t o t r ade t h eir a b i l i t y t o mast e r fo r a n ext r a p i n. t h e a d 799 2 is a sl a v e - o n ly de vice and us es t h e smbus a l er t t o si gn a l th e h o s t d e v i ce th a t i t w a n t s t o talk . th e s m b u s aler t o n t h e ad7992 is us ed as a n o u t-o f -con v e rsio n- r a n g e i n di ca to r (a lim i t viol a t ion i ndic a to r ) . the aler t pin has a n o p e n - d r a in co nf igura t ion t h a t a l lo ws t h e aler t ou t p u t s o f s e v e ral ad7 992s t o be wir e -and e d t o g e t h er w h en t h e aler t p i n is ac t i ve lo w . d0 o f t h e co nf igura t io n r e g i st er is us e d to s e t t h e ac t i v e p o la r i ty o f t h e aler t ou t p u t . the p o wer - u p defa u l t is ac t i v e l o w . th e ale r t f u n c t i on can b e dis a b l e d o r enab le d b y s e t t i n g d2 o f t h e conf igur a t io n r e g i ster t o 0 o r 1, r e s p ec ti v e l y . t h e h o s t devi ce ca n p r oce s s t h e a l er t i n t e rr u p t a n d s i m u l - ta n e o u s l y acce ss al l s m b u s al er t de vices thro ug h t h e aler t r e s p o n se ad d r e s s . o n l y th e device th a t p u ll ed t h e a l er t l o w ack n o w le dges t h e ar a (a ler t r e sp o n s e ad dr ess ) . i f m o r e t h an o n e de vice p u l l s t h e aler t p i n lo w , t h e hig h est p r io r i ty (lo w es t addr ess) d e vice wi n s co m m uni c a t io n r i g h ts v i a st anda r d i 2 c a r b i t r a t io n d u r i n g t h e sla v e addr es s t r a n sfer . the aler t o u t p u t b e com e s ac t i v e w h e n t h e v a l u e in t h e co n v ersio n r e s u l t r e g i s t er exce e d s t h e val u e in t h e d a t a hi g h r e g i s t er o r fal l s b e lo w t h e val u e in t h e d a t a low re g i ste r f o r a s e lec t e d c h a n nel . i t is r e s e t w h en a wr i t e o p era t io n t o t h e co nf igura t io n r e g i s t er s e ts d1 t o a 1, o r w h en t h e co n v ersion r e s u l t r e t u r n s n ls bs b e lo w o r a b o v e t h e v a l u e s t o r e d i n t h e da t a hi gh r e g i s t er o r d a t a low re g i ste r , re sp e c t i vely . n i s t h e val u e i n t h e h y st er esis r e g i s t er (s e e t h e l i mi t re g i s t ers s e c t ion). the aler t o u t p u t r e q u ir es an ext e r n al p u l l -u p r e sis t o r t h a t ca n b e co nn e c t e d t o a v o l t a g e di f f er en t f r o m v dd prov i d e d t h e max i m u m vol t age ra t i n g o f t h e aler t ou t p u t p i n is n o t exce e d e d . th e v a l u e o f t h e p u l l - u p r e sis t o r dep e n d s on t h e ap p l i c at i o n , b u t s h o u l d b e a s l a r g e a s p o s s i b l e t o av o i d e x c e s s i v e sink c u r r en ts a t t h e aler t o u t p u t . pl a c ing the ad7992-1 int o high speed mode h i g h s p eed m o d e co mm un ica t i o n co mm en ce s a f t e r th e m a s t er a d d r esses all de vi ces co nn e c t e d t o th e b u s w i t h th e m a s t er co d e , 00001x x x , t o indic a t e tha t a hig h s p e e d m o de tra n sf er is t o b e g i n. n o d e v i c e co nne c t e d to t h e b u s is a l lo w e d to ack n o w l- e d g e t h e hig h sp e e d mas t er co de; t h er efo r e , t h e co de is fol l o w e d b y a n o t ackno w le dg e (s e e f i g u r e 30). the mas t er m u s t t h en is s u e a r e p e a t e d s t a r t fol l o w e d b y t h e de vice addr es s wi t h a r/ w b i t. th e s e le c t e d de v i ce t h e n ackn o w le dg es i t s addr es s. al l de v i ces co n t in ue t o o p era t e in hig h s p e e d mo de un t i l t h e mas t er is s u es a s t o p con d i t ion. w h en t h e s t o p co n d i t ion is i s s u ed , t h e device s all r e t u rn t o fa s t m o de . the addre ss selec t ( a s) pin the addr es s s e l e c t p i n on t h e ad7992 is us ed to s e t t h e i 2 c addr es s f o r the ad7992 device . the as p i n can be tie d t o v dd , t o a g nd , o r lef t f l o a tin g . the s e le c t ion sh o u ld be made as c l os e as p o ssi b le t o t h e as p i n; a v o i d ha vin g lo n g t r acks i n t r o d uc in g ext r a ca p a c i t a n c e o n t o t h e pin. this is i m p o r t an t fo r t h e f l o a t s e l e c t i o n, b e c a u s e t h e a s pi n h a s to ch arge to a mi dp oi n t af te r t h e s t a r t b i t d u r i n g t h e f i rs t addr es s b y t e . e x t r a ca p a ci t a n c e o n th e a s p i n in cr e a se s t h e tim e ta k e n t o c h a r g e t o th e m i d p o i n t a nd ma y c a us e a n i n co r r e c t de c i sio n o n t h e de v i ce ad dr ess. w h en t h e as p i n is lef t f l o a tin g , th e ad7992 c a n w o rk wi th a ca p a ci t i v e lo ad u p t o 40 pf . sda ack. by ad7992 start by master hs-mode master code serial bus address byte nack 19 1 9 0 1 a2 a1 a0 x x 1 0 0 0 scl 0 0 a3 x sr fast mode high speed mode 03263-0-011 f i gure 3 0 . p l a c i n g t h e p a r t i n to hi gh s p eed m o de
ad7992 rev. 0 | page 25 of 28 modes of opera tion w h en s u p p lies a r e f i rs t a p p l ie d t o th e ad7992, th e ad c p o w e rs u p in s l e e p m o de and n o r m al l y r e ma in s in this s h ut do w n s t a t e w h i l e n o t con v e r t i n g . th er e a r e t h r e e dif f er en t m e tho d s o f ini t ia tin g a con v ersio n o n t h e ad79 92. mode 1u s ing the c o nv st pi n a co n v ersion can b e ini t ia t e d on t h e ad7992 b y p u lsin g th e co n v s t sig n al . th e con v ersio n clo c k fo r t h e p a r t is in t e r n al l y g e n e ra t e d s o n o ext e r n al c l o c k is r e q u ir ed , excep t w h en r e ading f r om or w r it i n g to t h e i 2 c s e ri a l p o rt . o n th e r i s i n g e d g e o f co n v s t , th e ad7992 beg i n s t o p o w e r u p (s ee p o in t a in f i g u re 3 1 ) . t h e p o we r - up t i me f r om sh utd o w n mo d e for t h e ad7992 is a p p r o x ima t e l y 1 s; th e co n v s t sig n al m u st r e ma in high f o r 1 s f o r th e p a r t t o p o w e r u p f u ll y . co n v s t c a n be b r o u gh t lo w a f t e r th i s tim e . th e fall i n g ed g e o f th e co n v s t sig n a l places t h e t r ack-and- h o l d i n t o h o l d m o de; a co n v ersio n is a l s o ini t i a t e d a t t h is p o in t (p o i n t b in f i gur e 31). w h en t h e con versio n is co m p l e t e , a p p r o x ima t e l y 2 s la t e r , t h e p a r t r e t u r n s t o sh u t do wn (p oin t c in f i gur e 31) a nd r e ma in s t h er e u n t i l t h e next r i sin g e d g e o f co n v s t . th e mas t er ca n t h e n r e ad t h e a d c t o ob t a in t h e co n v ersion r e su l t . th e addr es s p o in t e r r e g i s t er m u s t b e p o in t i ng t o t h e co n v ersio n r e s u l t r e g i s t er in o r der t o r e ad b a ck t h e co n v ersion r e su l t . if t h e co n v s t p u ls e do es n o t r e main hi g h fo r m o r e t han 1 s, th e fallin g ed g e o f co n v s t s t il l ini t ia t e s a co n v ersio n , b u t t h e r e s u l t is in val i d bec a us e t h e ad7992 is n o t f u l l y p o w e r e d u p w h en t h e co n v e r sio n t a k e s plac e . t o ma in t a i n t h e p e r f o r ma n c e o f th e ad7992 in this m o de , i t is r e co mm ended tha t t h e i 2 c b u s is q u iet w h en a co n v ersio n is t a k i n g pl ace . the c y cle t i m e r r e g i s t er a nd c o mman d bi ts c4 t o c1 in t h e addr es s p o in t e r r e g i s t er sh o u ld co n t a i n al l 0s w h e n o p era t in g th e ad7992 in t h is m o de 1. the co n v s t pi n s h ou l d b e t i e d lo w fo r a l l o t h e r m o des o f o p era t io n. pr io r t o in i t ia t i n g a co n v ersio n in t h is m o de , a wr i t e t o t h e co nf igu r a t io n r e g i st er is n e e d e d t o s e le c t th e c h ann e l f o r co n v ersio n . t o s e le c t bo t h in p u t cha nnels fo r co n v ersio n , s e t d5 a nd d4 i n t h e c o nf igur a t io n r e g i s t er t o 1. the ad c s e r v ices e a ch cha n ne l i n t h e s e q u e n c e wi t h e a ch co n v s t pu l s e. on ce t h e con v ersio n is co m p lete , t h e mast er can addr es s t h e ad7992 t o r e ad th e con v ersion r e s u l t . i f f u r t h e r co n v ersio n s a r e r e q u i r e d , th e sc l l i n e c a n b e ta k e n h i gh w h i l e t h e co n v s t s i gn al i s p u l s ed ; th en a n a d d i ti o n al 18 sc l p u l s e s a r e r e q u i r ed t o r e ad t h e n e xt co n v ersio n r e su l t . 11 9 sca 9 s 7-bit address ra first data byte (msbs) a second data byte (lsbs) 9 p sda t power-up b a c t convert 03473-0-032 convst a f i g u re 31. m o d e 1 o p er at ion
ad7992 rev. 0 | page 26 of 28 mode 2 C c o mmand m o de m o de 2 a l l o w s a c o n v e r s i on to b e a u tom a t i c a l l y i n i t i a te d a n y t i m e a wr i t e o p e r a t io n o c c u rs. i n o r der to us e t h is m o de, c o mmand bi ts c2 to c1 in t h e addr ess p o in ter b y te, sh o w n in t a b l e 7, m u st b e p r o g r a mm e d . c o mmand bi ts c4 a nd c3 a r e n o t us e d an d sho u ld co n t ain ze r o s a t a l l t i m e s. t o s e le c t a cha n ne l fo r co n v ersi o n in m o de 2, s e t t h e co r r es- p o ndi n g cha n nel co mmand b i t in t h e a d dr ess p o in ter b y te (s ee t a b l e 24). t o s e lec t bo t h a n alog in p u t c h a n ne ls f o r co n- versio n, s e t b o t h c1 an d c2 to 1. w h e n a l l fo ur co mma nd b i ts a r e 0, t h is m o de is n o t us e d . f i gur e 28 i l l u s t ra t e s a 2 - b y t e r e ad o p era t io n f r o m t h e con v er - sio n r e s u l t r e g i st er . p r io r t o t h e r e ad o p era t io n, en s u r e t h a t t h e addr es s p o in t e r is p o in t i n g t o t h e co n v ersion r e su l t r e g i s t er . w h en t h e co n t e n ts o f t h e addr e s s p o i n t e r r e g i s t er a r e b e i n g lo aded , if c o mma nd b i ts c2 or c1 a r e s e t, t h e ad7992 beg i n s to p o w e r u p and co n v er t u p o n t h e s e le c t e d ch annel(s). p o w e r - u p beg i n s on t h e f i f t h scl f a l l in g edg e o f t h e addr es s p o in t b y te (s ee p o in t a in f i gur e 32). t a b l e 24 sh o w s t h e c h a nne l s e lec t ion in t h is mo de v i a c o mmand bi ts c1 a nd c2 i n t h e a ddr ess p o in t e r r e g i s t er . the wake-u p and co n v ersio n t i me t o g e t h er s h o u l d t a k e ap p r ox i m at e l y 3 s , a n d t h e c o n v e r s i o n b e g i n s w h en t h e last c o mma nd bi t, c 1 , has b e e n clo c k e d i n mi d w a y t h r o ug h t h e wr i t e t o t h e addr ess p o in t e r r e g i s t e r . f o l l o w in g t h is, t h e a d 799 2 m u st b e ad dr e s s e d a g a i n to tel l i t t h a t a r e a d o p era t ion is r e quir e d . t h e r e ad t h e n t a k e s place f r o m t h e co n v ersio n r e s u l t r e g i s t er . this r e ad access es t h e r e s u l t f r o m t h e co n v ersion s e le c t e d v i a t h e c o mma nd b i ts . i f c o mmand bi ts c2, c1 a r e s e t to 1,1, a 4-b y t e r e ad is n e ces s a r y . the f i rs t r e ad acces s es t h e da t a f r o m t h e co n v ersio n o n v in 1. w h il e th i s r e ad t a k e s plac e, a con v ersio n o c c u rs o n v in 2. the s e co nd r e ad a c c e s s e s th i s d a ta fr o m v in 2. f i g u r e 33 s h o w s h o w this m o de o p era t es. a f te r t h e c o n v e r s i on re su lt h a s b e e n re a d , a n d i f f u r t he r re a d b y t e s a r e is s u e d , t h e ad c con t i n uo us l y co n v er t s o n t h e s e le c t e d in p u t cha n ne l(s ) . this has t h e e f fe c t o f in cr e a sin g t h e o v era l l th r o ugh p u t ra t e o f th e ad c . w h en op era t ing th e ad7992 -1 in m o de 2 wi t h hig h s p ee d m o de , 3.4 m h z scl, t h e con v ersio n ma y n o t be co m p let e b e fo r e t h e mas t er t r ies t o r e ad t h e con v ersion r e s u l t . i n t h is cas e , t h e ad79 92-1 h o lds t h e s c l lin e lo w d u r i n g t h e a c k clo c k a f t e r t h e re ad addr es s u n t i l t h e con v ersio n is co m p le t e . w h en t h e con v ersio n is co m p l e t e , t h e ad7992 -1 r e leas es t h e scl li n e and t h e mas t er can t h en r e ad t h e con v ersio n r e s u l t . af t e r a co n v ersi o n is in i t ia te d i n t h is m o de b y s e t t in g t h e co mman d b i ts in t h e addr es s p o in t e r b y t e , if t h e ad7992 r e cei v es a s t o p o r n a ck f r o m th e mas t er , t h e ad7992 s t o p s co n v er ting. tab l e 24. a d d r ess poin ter by tecommand bits c2 c1 analog input c h annel 0 0 no conversi on 0 1 conversi on on v in 1 1 0 conversi on on v in 2 1 1 conversi on on v in 1 follo wed by conver sion o n v in 2 9 11 a 9 s wa a sr ra a second data byte (lsbs) first data byte (msbs) command/address point byte 7-bit address 7-bit address a sda 11 9 scl sda scl 9 9 sr/p 8 ack by ad7992 ack by ad7992 ack by master nack by master ack by ad7992 03263-0-012 f i g u re 32. m o d e 2 o p er at ion
ad7992 rev. 0 | page 27 of 28 9 11 scl 9 s 7-bit address wa command/address point byte a s d a first data byte (msbs) a second data byte (lsbs) first data byte (msbs) second data byte (lsbs) a sr 7-bit address ra sda 9 9 1 1 scl 9 8 ack by ad7992 ack by ad7992 ack by master ack by master ack by master ack by ad7992 a 9 9 result from ch1 result from ch2 a/a 03263-0-013 f i gure 33. mod e 2 s e quence o p e r at ion mode 3 a u t o ma tic c y cle mode an a u toma t i c c o n v ersio n c y cle ca n b e s e le c t e d a nd ena b le d b y wr i t in g a val u e to t h e c y cle t i m e r r e g i s t er . a co n v ersio n c y cle in t e r v al can b e s e t u p o n the ad7992 b y p r og ra mmin g t h e r e le van t b i ts in t h e 8- b i t c y cle t i m e r r e g i ster , as de co de d i n t a b l e 23. onl y t h e 3 ls b s a r e us ed; t h e 5 ms bs s h o u l d co n t a i n 0s (s e e t h e sam p le d e l a y an d bi t t r ial d e la y s e c t io n). w h en t h e 3 ls bs o f t h e re g i s t er a r e p r og ra mme d w i t h an y co nf igura t io n o t h e r t h an al l 0s , a co n v ersio n t a k e s place e v er y x m s ; t h e c y cle in t e r v a l , x, dep e n d s on t h e co nf igura t io n o f t h es e t h r e e b i ts in t h e c y cle t i m e r r e g i s t er . th er e ar e s e v e n dif f er e n t c y cle t i me in t e r v als t o ch o o s e f r o m , as s h o w n in t a b l e 23. on ce t h e co n v ersio n ha s t a k e n place, t h e p a r t p o w e rs do w n a g a i n u n t i l t h e n e xt co n v ersio n o c c u rs. t o exi t t h is m o de of o p era t io n, t h e us er m u s t p r og ra m t h e 3 ls b s o f t h e c y cle t i m e r r e g i s t er t o c o n t ai n a l l 0 s . for c y cl e i n te r v a l opt i ons , s e e t a bl e 2 3 . t o s e le c t a cha n nel(s) fo r o p er a t io n i n c y cle m o de, s e t t h e co r r esp o n d in g cha nnel b i t(s), d 5 to d4, o f t h e c o nf igur a t io n r e g i s t er . i f m o r e t h a n on e cha n ne l b i t is s e t i n t h e co nf igura t io n r e g i s t er , t h e a d c a u t o ma t i cal l y c y cles t h r o ug h t h e cha n n e l s e qu e n c e , st ar t i ng w i t h t h e l o we st chan nel. o n c e t h e s e qu e n c e is co m p let e , t h e ad c s t a r ts con v er t i n g o n t h e l o w e s t cha n ne l a g a i n , co n t i n uin g t o loo p th r o ugh t h e seq u en ce un til th e c y c l e t i m e r r e g i st er c o n t e n ts a r e s e t to a l l 0s. this mo de is us ef u l fo r mon i tor i ng s i g n a l s , su ch a s b a tt e r y volt age and te m p e r a t u r e, aler t i n g o n l y w h e n t h e li mi ts ar e viol a t e d .
ad7992 rev. 0 | page 28 of 28 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba f i gure 34. 1 0 -l ead m i ni s m al l o u tl ine p a ck ag e [msop ] (r m - 10) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model 1 temperature r a nge linearity error 2 (max) package option package descri ption branding AD7992BRM-0 C40c to +125c 1 lsb rm-10 10-lead msop c10 AD7992BRM-0r eel C40c to +125c 1 lsb rm-10 10-lead msop c10 ad7992brmz-0 3 C40c to +125c 1 lsb rm-10 10-lead msop c2q ad7992brmz-0 r eel 3 C40c to +125c 1 lsb rm-10 10-lead msop c2q ad7992brm-1 C40c to +125c 1 lsb rm-10 10-lead msop c11 ad7992brm-1r eel C40c to +125c 1 lsb rm-10 10-lead msop c11 ad7992brmz-1 3 C40c to +125c 1 lsb rm-10 10-lead msop c2s ad7992brmz-1 r eel 3 C40c to +125c 1 lsb rm-10 10-lead msop c2s eval-ad7992c b stand-alone evaluation board 1 the ad7992-0 sup p orts standard an d fast i 2 c interface m o des. the ad7992-1 support s standar d , fast, and high sp eed i 2 c i n t e rfa c e m o de s. 2 linearity error here re fer s to inte gral n o nl ine a rity. 3 z = pb-free part. purch a se of li c e n s e d i 2 c com p on en t s o f an a l og d e vi ces or on e of i t s subli c en s e d as soci a t ed c o m p a n i e s con v eys a li cen s e for t h e purch a ser un der t h e ph i li p s i 2 c p a te nt rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2005 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d03263C0C 1/05(0)

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